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| CY2509/10 Spread AwareTM, Ten/Eleven Output Zero Delay Buffer Features * Spread AwareTM--designed to work with SSFTG reference signals * Well suited to both 100- and 133-MHz designs * Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL outputs * 50 ps typical peak cycle-to-cycle jitter * Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs * 3.3V power supply * On board 25 damping resistors * Available in 24-pin TSSOP package * Improved tracking skew, but narrower frequency support limit when compared to W132-09B/10B Key Specifications Operating Voltage: ................................................3.3V10% Operating Range: ....................... 40 MHz < fOUT < 140 MHz Cycle-to-Cycle Jitter: ................................................ <100 ps Output to Output Skew: ........................................... <100 ps Phase Error Jitter:..................................................... <100 ps Block Diagram FBIN CLK Pin Configurations PLL FBOUT Q0 Q1 Q2 AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK AVDD VDD Q9 Q8 GND GND Q7 Q6 Q5 VDD FBIN CY2510 OE0:4 Q3 OE Q4 Q5 OE5:8 Q6 Q7 Q8 Q9 Configuration of these blocks dependent upon specific option being used AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE0:4 FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK AVDD VDD Q8 Q7 GND GND Q6 Q5 VDD OE5:8 FBIN CY2509 Cypress Semiconductor Corporation Document #: 38-07230 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised July 01, 2005 CY2509/10 Pin Definitions Pin Name CLK FBIN Pin No. (2509) 24 13 Pin No. (2510) 24 13 Pin Type I I Pin Description Reference Input: Output signals Q0:9 will be synchronized to this signal. Feedback Input: This input must be fed by one of the outputs (typically FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input. Integrated Series Resistor Outputs: The frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. Each output has a 25 series damping resistor integrated. Integrated Series Resistor Output: The frequency and phase of the signal provided by this pin will be equal to the reference signal if properly laid out. This output has a 25 series damping resistor integrated. Feedback Output: This output has a 25 series resistor integrated on chip. Typically it is connected directly to the FBIN input with a trace equal in length to the traces between outputs Q0:9 and the destination points of these output signals. Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. Analog Ground Connection: Connect to common system ground plane. Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. Ground Connections: Connect to common system ground plane. Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) all outputs are disabled to a LOW state. Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state. Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state. enough to meet all the requirements of the memory and logic on the DIMM. The CY2509/10 takes in the signal from the motherboard and buffers out clock signals with enough drive to support all the DIMM board clocking needs. The CY2509/10 is also designed to meet the needs of new PC133 SDRAM designs, operating to 133 MHz. The CY2509/10 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay buffers which are not designed to pass this feature through may cause skewing failures. Output enable pins allow for shutdown of output when they are not being used. This reduces EMI and power consumption. Q0:8 3, 4, 5, 8, 9, 16, 17, 20, 21 n/a 3, 4, 5, 8, 9, 15, 16, 17, 20 21 O Q9 O FBOUT 12 12 O AVDD AGND VDD GND OE OE0:4 OE5:8 23 1 2, 10, 15, 22 6, 7, 18, 19 n/a 11 14 23 1 2, 10, 14, 22 6, 7, 18, 19 11 n/a n/a P G P G I I I Overview The CY2509/10 is a PLL-based clock driver designed for use in dual inline memory modules. The clock driver has output frequencies of up to 133 MHz and output to output skews of less than 250 ps. The CY2509/10 provides minimum cycle-tocycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications. The current generation of 256- and 512-megabyte memory modules needs to support 100-MHz clocking speeds. Especially for cards configured in 16x4 or 8x8 format, the clock signal provided from the motherboard is generally not strong Document #: 38-07230 Rev. *C Page 2 of 6 CY2509/10 1 AGND VDD Q0 Q1 CLK 24 AVDD 23 VDD 22 Q9 21 20 VDD 0.1F 2 3 4 5 6 7 8 9 0.1F FB 3.3V 0.1F 10 F VDD 10 F FB CY2510 Q2 GND GND Q3 Q4 VDD OE Q8 GND 19 GND 18 Q7 Q6 Q5 17 16 15 VDD 0.1F 10 11 12 VDD 14 FBIN 13 FBOUT 0.1F VDD Figure 1. Schematic Spread AwareTM Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs." If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. Reference Signal Feedback Input How to Implement Zero Delay Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. Since the PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feed back and the FBIN input to the PLL. Zero Delay Buffer ASIC/ Buffer A Figure 2. Six Output Buffers in the Feedback Path Document #: 38-07230 Rev. *C Page 3 of 6 CY2509/10 Absolute Maximum Ratings [1] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi. tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation DC Electrical Characteristics: TA =0C to 70C, VDD = 3.3V 10% Parameter IDD VIL VIH VOL VOH IIL IIH Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current IOL = 12 mA IOH = -12 mA VIN = 0V VIN = VDD Test Condition Unloaded, 100 MHz Min. - - 2.0 - 2.1 - - Typ. - - - - - - - Max. 200 0.8 VDD+0.3 0.8 - 50 50 Unit mA V V V V A A AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 10% Parameter fOUT tR tF tICLKR tICLKF tPEJ tSK tD tLOCK tJC Description Output Frequency Output Rise Time Output Fall Time Input Clock Rise Input Clock Fall Time[2] Variation[3, 4] Measured at VDD/2 All outputs loaded equally 30-pF load Power supply stable Time[2] 30-pF Test Condition load[5] 0.8V to 2.0V, 30-pF load 2.0V to 0.8V, 30-pF load Min. 40 - - - - -350 -100 43 - - Typ. - - - - - 0 0 50 - 50 Max. 140 2.1 2.5 4.5 4.5 350 100 58 1.0 100 Unit MHz ns ns ns ns ps ps % ms ps CLK to FBIN Skew Duty Cycle PLL Lock Time Output to Output Skew Jitter, Cycle-to-Cycle Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Longer input rise and fall time will degrade skew and jitter performance. 3. Skew is measured at VDD/2 on rising edges. 4. Duty cycle is measured at VDD/2. 5. Production tests are run at 133 MHz. Document #: 38-07230 Rev. *C Page 4 of 6 CY2509/10 Ordering Information Ordering Code CY2509ZC-1 CY2509ZC-1T CY2510ZC-1 CY2510ZC-1T Lead-free CY2509ZXC-1 CY2509ZXC-1T CY2510ZXC-1 CY2510ZXC-1T 24-pin TSSOP 24-pin TSSOP - Tape and Reel 24-pin TSSOP 24-pin TSSOP - Tape and Reel Commercial Commercial Commercial Commercial Package Type 24-pin TSSOP 24-pin TSSOP - Tape and Reel 24-pin TSSOP 24-pin TSSOP - Tape and Reel Temperature Range Commercial Commercial Commercial Commercial Package Drawing and Dimensions 24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 PIN 1 ID 1 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 24 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. GAUGE PLANE 0.076[0.003] 0.25[0.010] BSC 0-8 0.85[0.033] 0.95[0.037] 7.70[0.303] 7.90[0.311] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85119-*A Spread Aware is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07230 Rev. *C Page 5 of 6 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2509/10 Document History Page Document Title: CY2509/10 Spread AwareTM, Ten/Eleven Output Zero Delay Buffer Document Number: 38-07230 REV. ** *A *B *C ECN NO. 110495 122844 352015 385383 Issue Date 01/07/02 12/14/02 See ECN See ECN Orig. of Change SZV RBI RGL RGL Description of Change Change from Spec number: 38-00914 to 38-07230 Power up requirements added to Operating Conditions Information Added Lead-free devices Added typical jitter and max. VIH numbers Minor Change: Replaced the wrong package drawing Document #: 38-07230 Rev. *C Page 6 of 6 |
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